1. Field of the Invention
The present invention relates to a display device comprising a display panel using ac discharge.
2. Description of the Background Art
As a conventional display panel using ac discharge, an ac plasma display panel (hereinafter referred to as a "PDP") has been well known. The ac PDP includes a two-electrode opposite discharge type and a three-electrode surface discharge type. We will first describe the two-electrode opposite discharge type. FIG. 17 is an exploded perspective view showing the structure of a conventional ac PDP, which is described for example in Owaki et. al., "Plasma Display", Kyoritsu Publishing, p. 21 (hereinafter referred to as a "reference 1"). A conventional ac PDP 1 is produced by bonding two glass substrates 2 on which various members are formed. The two glass substrates 2 are provided in parallel with a predetermined gap therebetween. Assuming that the surface of the glass substrate 2 on the gap side is the inner surface and the surface on the opposite side is the outer surface, sealing glass 6 is formed on the inner periphery of the inner surface of the glass substrate 2. A gap surrounded by the sealing glass 6 is sealed and filled with discharge gas. Hereinafter the glass substrate 2 closer to a display viewer is referred to as a front glass substrate 2 and the other as a rear glass substrate 2. Strip electrodes 3a on the inner surface of the front glass substrate 2 are usually transparent electrodes. This is for the purpose of admitting light, which is produced in the gap between the two glass substrates 2, to the front through the front glass substrate 2. On the inner surface of the rear glass substrate 2, strip electrodes 3b are formed which are orthogonal to the electrodes 3a when the glass substrate 2 is seen through from the front. The strip electrodes 3a formed in an area surrounded by the sealing glass 6 on the front glass substrate 2 are covered with a dielectric layer 4, which is then covered with a protective layer 5. Similarly, the rear glass substrate 2 is provided with a dielectric layer 4 which covers the electrodes 3b and a protective layer 5 which covers the dielectric layer 4.
For monochrome display using emitted colors of discharge gas itself, discharge is induced at the intersections of the strip electrodes 3a, 3b in the above structure. Color display, on the other hand, requires additional three kinds of phosphors which emit red, green, and blue lights, respectively, depending on the light (e.g., ultraviolet ray) produced by discharge, besides the above structure. For color display, each intersection of the electrodes 3a, 3b is coated with a phosphor of one color and three emitted colors of adjacent phosphors are mixed to be a point (pixel) representing various colors. The combination of such points allows acquisition of any desired image in color display.
Now, we will describe the driving principle of a conventional two-electrode opposite discharge type ac PDP. FIG. 18 shows variations in the voltage across electrodes, variations in the wall voltage, and the waveform of light emission, all in the two-electrode opposite discharge type ac PDP. These waveforms are disclosed for example in the above reference 1. The wall voltage is a voltage generated by charge accumulated on the walls of discharge cells. The voltage waveform across electrodes varies with three periods, i.e., address period (writing), sustained discharge period (sustaining), and reset period (erasing), even in one cycle of a driving sequence. The amplitude baselines of a write pulse WPu, a sustain voltage pulse SPu, and an erase pulse EPu in the address, sustain discharge, and reset periods, respectively, are 0V. The write pulse WPu has a write voltage Vwr larger than a firing voltage Vf in amplitude. The sustain voltage pulse SPu has a sustain voltage Vs larger than a discharge sustain voltage Vsm in amplitude. The erase pulse EPu has an erase voltage Ve in amplitude.
With the wall voltage brought to 0V by the erase pulse, a driving sequence starts with no discharge and no light emission. When the write pulse WPu larger in amplitude than the sustain voltage pulse SPu is applied across the electrodes 3a, 3b, discharge occurs in cells, which produces light. Then, charge is transferred to the surface of the dielectric layer 4 which covers the electrodes 3a, 3b, This causes charge-up and a reverse voltage in the cells, thus stopping discharge. At this time, the accumulated charge on the surface of the dielectric layer 4 generates a wall voltage Vw. In cells where no write pulse WPu is applied and no write discharge occurs, the wall voltage Vw does not appear.
After the address period, a sustain voltage pulse HPu (-Vs), opposite in polarity from the write pulse WPu, is applied across the electrodes 3a, 3b. This generates a voltage equal to a sum of the wall voltage Vw and the sustain voltage Vs from the outside, in the discharge cells. The reference Vw indicates the value of the wall voltage as well as the wall voltage itself. The resultant voltage (.vertline.Vw.vertline.+.vertline.Vs.vertline.) is large enough to induce discharge, so discharge occurs again to produce light. At this time, a wall voltage Vw, opposite in polarity from that in writing, is developed in the discharge cells.
Further, a sustain voltage pulse SPu (Vs), opposite in polarity from that before a half cycle, is applied across the electrodes 3a, 3b. This generates a voltage equal to the sum of the wall voltage Vw and the sustain voltage Vs (.vertline.Vw.vertline.+.vertline.Vs.vertline.), whereby discharge occurs again. During the sustain discharge period, every application of the sustain voltage pulse SPu generates a potential of .vertline.Vw.vertline.+.vertline.Vs.vertline. and discharge is repeated. The discharge repeated during the sustain discharge period is referred to as "sustain discharge". The sustain discharge stops when the wall voltage Vw becomes almost 0 V due to weak discharge caused by the erase pulse EPu in the discharge cells. The erase pulse EPu includes two types: wide and low-voltage type which is large in width and small in amplitude; and narrow and high-voltage type which is small in width and large in amplitude. Here, high/low in the voltage indicates that the voltage is higher or lower than the sustain voltage Vs, respectively. The former type is the driving condition of the aforementioned two-electrode opposite discharge type ac PDP, and the latter type is the driving condition of a three-electrode surface discharge type ac PDP which will be described later.
It is found from the above description that it is important to erase the wall voltage down to 0V in all discharge cells before the address (write) discharge in the conventional display panels. If the wall voltage Vw in the discharge cells before the address discharge is not 0 V, undesirable discharge may occur in the unselected cells or necessary discharge may not occur in the selected cells. This insufficient erasing is one of the big factors behind reduction in the driving margin.
Now, we will describe a conventional driving principle of a three-electrode surface discharge type ac PDP. FIG. 19 shows voltage waveforms across electrodes to explain how to drive the PDP, which is described for example in Japanese Patent Laid-open No. P07-160218A. As shown, voltages of different waveforms are applied to three types of electrodes to drive a PDP. The three types of electrodes include column electrodes Wj, row electrodes Yk, and a common row electrode X, where the subscripts j, k are natural numbers indicating the sequences of the column electrodes W and the row electrodes Y. The driving principle of the three-electrode surface discharge type ac PDP is identical to that of the aforementioned two-electrode opposite discharge type ac PDP, so it can be applied to the two-electrode opposite discharge type ac PDP without problems. Under the present circumstances, the three-electrode surface discharge type ac PDP is in the mainstream and more suitable for matrix display using ac discharge. For display of a moving image, different static images are displayed every 1/60 second, for example. Here the display period for a single static image is a single frame. To control gradation, a single frame should be divided into a plurality of sub-fields. A single sub-field is the minimum unit of a frame. For 256-level gradation, for example, one frame is divided into eight sub-fields which emit light in the proportions of 2.sup.0 :2.sup.1 :2.sup.2 :2.sup.3 :2.sup.4 :2.sup.5 :2.sup.6 :2.sup.7, respectively. Each sub-field consists of three periods. The first period is a reset period to handle two important matters: (1) to erase and reset wall charge left in the cells after discharge occurs in each sub-field (i.e., erasing reset); and (2) to induce discharge in all the cells at least one time in each frame to supply priming particles for smoothing the address discharge into the panel (i.e., priming reset). The voltage pulse for the erasing reset, which is applied across electrodes, is different from that for the priming reset. That is, the voltage for the erasing reset is suppressed lower than that for the priming reset to suppress an increase in luminance in dark display (i.e., contrast reduction). The voltages for the erasing reset and for the priming reset are about 230 V and 330 V, respectively. While the PDP shown in FIG. 18 is a self-erase type without applying the erase pulse, the PDP in FIG. 19 performs erasing at the time when the voltage pulses P.sub.wp, P.sub.xp changes from its peak value to the baseline for the priming reset.
The second period is an address period, wherein wall charge (voltage) is selectively developed in the matrix of cells. By inducing discharge between orthogonal column and row electrodes Wj, Yk in selected cells, wall charge can be developed in any desired cell. The voltage across electrodes in selected cells is about 230 V and the same in unselected cells is about 170 V.
The third period is a sustain discharge period to repeat discharge. Here the sustain discharge occurs only in the cells selected in the address period. During the sustain discharge period, sustain discharge occurs across row electrode Yk and the common row electrode X. The voltage across the row electrode Yk and the common row electrode X is about 180 V. The intensity of light in cells increases with the number of times discharge occurs.
We will now briefly describe structural advantages of the three-electrode surface discharge type ac PDP. The row electrodes Yk, X are transparent electrodes formed on the inner surface of the front glass substrate. The column electrodes Wj formed on the inner surface of the rear glass substrate are orthogonal to the row electrodes Yk, X when seen through the front glass substrate and the rear glass substrate. In the three-electrode surface discharge type, phosphors are formed only on the rear glass substrate and sustain discharge occurs between the two row electrodes Yk, X on the front glass substrate. This allows the phosphors to be kept from discharge, thus preventing deterioration of the phosphors. Accordingly, the longevity of the PDP is increased. In the two-electrode opposite discharge type, on the other hand, it is difficult to repeat numbers of short-cycle sustain discharges while keeping phosphors therefrom. Therefore, the structure of the three-electrode surface discharge type ac PDP is suitable for color display using light emission from phosphors.
In the conventional display panels, at least one priming reset discharge is necessary in each frame in order to fill all the cells with priming particles to thereby reduce the voltage generated by the address discharge. However, light emission from the priming reset discharge results in contrast degradation.
Further, an extremely high priming reset voltage (e.g., 330 V) is applied across the electrodes at least one time in each frame. This increases stress on the dielectric layer and thus degrades that layer, resulting in deterioration in the reliability of a PDP.
In the conventional display panels, the address operation cannot be done without discharge. To start discharge, an address time of about 3 .mu.sec is necessary for each cell because of discharge delay of about 1 .mu.sec. For a 128- by 128 cell matrix of ac discharge type display panel which is capable of controlling 256-level gradation, for example, the necessary address time is given by 3 .mu.sec.times.128 lines.times.8 sub-fields, i.e., 3.072 msec. When a single frame is 1/60 second and the maximum number of light emissions in a single frame is 8192, the sustain frequency is given by 4096 sustain cycles.div.(1.div.60-3.072.times.10.sup.-3), i.e., 302 kHz. If the address time can be eliminated, the sustain frequency becomes 4096 sustain cycles.times.60, i.e., 246 kHz. Since a desirable sustain frequency for sustaining discharge and generating the wall voltage with certainty is considered to be 250 kHz (sustain pulse width of over 2 .mu.sec), it is apparent that the above high-intensity display (8192 light emissions) is impossible when the write (address) time is 3 .mu.sec. For high-intensity display, thus, the write time must be shorten.
The conventional display panels require a voltage of about 230 V to induce address discharge. To generate that address voltage, an integrated circuit having a plurality of output pins for both row and column electrodes is used. This integrated circuit is sensitive to a large current since its allowable current value is low to increase the level of integration. Although the address discharge rarely causes a large current flow, in cases where large charge is abnormally accumulated on the barrier ribs of discharge cells or the surface of the dielectric layer, the application of voltage as large as 230 V in the address operation induces, along with internal charge, high-voltage discharge in the cells. This results in a large current. Large current may cause a malfunction in the part of the integrated circuit which are relevant to bits corresponding to the row and column electrodes. Such a malfunction will result in an inline defect on display for matrix display and a dot defect on display for static-driven display. In this fashion, address discharge may cause an abnormal current flow resulting in an undesirable display.
Furthermore, the conventional display panels ensure the driving margin by erasing the wall charge without fail in each sub-field. However, it is difficult to completely erase the wall charge in all the cells by erase discharge. Some positive or negative wall voltage is thus left even after the erase discharge. If the wall charge in all the cells can completely be erased, the range of the sustain voltage Vs becomes as follows: the minimum discharge sustain voltage (minimum voltage to maintain sustain discharge)&lt;Vs&lt;230 V (address voltage). This range is narrowed in proportion to the amount of remaining wall voltage after the erase discharge. This insufficient erasing of the wall voltage induces error discharge, thereby degrading image quality.